IGCSE Computer Science (0478)
Complete Revision Modules
1. Data Representation
Computers process all operational details using binary switches representing states of high and low voltage.
1.1 Number Systems (Binary, Denary, Hexadecimal)
- Binary: Base-2 number system using digits 0 and 1.
- Denary: Base-10 positional layout tracking digits 0 through 9.
- Hexadecimal: Base-16 structural representation using 0–9 and letters A–F (where A=10, B=11, C=12, D=13, E=14, F=15). Used by developers to make long binary sequences more human-readable.
1.2 Conversions & Binary Arithmetic
When executing binary addition, care must be taken with carry rules. If a value exceeds 8 bits inside an 8-bit register, an overflow error occurs.
| Operation | Rule Statement |
|---|---|
| 0 + 0 | 0 |
| 1 + 0 | 1 |
| 1 + 1 | 0 (Carry 1 to the next column) |
| 1 + 1 + 1 | 1 (Carry 1 to the next column) |
1.3 Text, Sound, and Image Storage
- Text: Character sets like ASCII (uses 7 or 8 bits per character) or Unicode (uses up to 32 bits, allowing global language characters).
- Images: Made of discrete pixels. Resolution is the total pixel concentration. Color Depth represents bits per pixel. File size changes with both values.
- Sound: Analog sound waves are sampled at fixed intervals. Higher Sampling Rate and Sample Resolution capture cleaner sound profiles but generate larger storage loads.
1.4 Data Compression
- Lossy Compression: Permanently discards less noticeable data paths (e.g., JPEG, MP3). The original raw state cannot be recovered.
- Lossless Compression: Compresses file footprints without discarding any data (e.g., RLE, zip). The original file can be perfectly reconstructed.
2. Data Transmission
Data transmission across networks requires precise structural validation rules.
2.1 Transmission Methods
- Serial vs Parallel: Serial transmits data bits sequentially over a single link wire. Parallel transmits multiple data bits simultaneously across parallel physical tracks, risking synchronization errors over long distances.
- Direction Configurations: Simplex (one direction only), Half-Duplex (both directions but only one side at a time), and Full-Duplex (simultaneous bidirectional paths).
2.2 Error-Checking Methods
- Parity Check: Adds a parity bit to an 8-bit block to make the count of '1's either even or odd. It cannot detect structural shifts if two bits flip simultaneously.
- Checksum: The sender computes a sum calculation on data payload packages. The recipient recalculates this sum value; mismatch blocks are re-requested.
- Cyclic Redundancy Check (CRC): Applies a mathematical division formula to data blocks to ensure transmission consistency.
- Echo Check: Recipient mirrors the received block back to the sender for cross-comparison. High bandwidth footprint.
- Automatic Repeat Request (ARQ): Uses acknowledgments and timeout windows to automatically resend corrupted or unacknowledged data blocks.
2.3 Encryption Layouts
Symmetric Encryption: Sender and recipient share an identical secret key for encryption and decryption. Asymmetric Encryption: Uses a publicly shared encryption key combined with a private decryption key kept strictly secure by the destination host.
3. Hardware & Architecture
Modern computers utilize the internal operational components of the Von Neumann model.
3.1 Von Neumann CPU Architecture
- Control Unit (CU): Directs memory routing and decodes execution instructions.
- Arithmetic Logic Unit (ALU): Performs logical evaluations and arithmetic processes.
- Registers: High-speed internal memory cells inside the CPU:
- Program Counter (PC): Tracks the execution memory address of the next system instruction.
- Memory Address Register (MAR): Temporarily holds the target storage address currently being accessed.
- Memory Data Register (MDR): Temporarily buffers the functional data item copied from or written to memory locations.
- Current Instruction Register (CIR): Holds the block instruction currently being decoded and executed by the CU.
- Accumulator (ACC): Stores the computational output results generated by the ALU.
3.2 The Fetch-Decode-Execute Cycle
- The CPU fetches the execution instruction pointing from the address inside the PC, copying it via the MAR and MDR into the CIR.
- The PC increments by 1.
- The CU decodes the instruction payload inside the CIR.
- The system executes the action, involving components like the ALU or memory if needed.
3.3 Input, Output, and Storage Media
- Input Devices: Barcode scanners, 2D/3D scanners, keyboards, microphones, digital cameras.
- Output Devices: LCD/OLED monitors, laser printers, inkjet printers, 3D cutters, actuators, speakers.
- Primary Memory: RAM (Volatile, read/write workspace) and ROM (Non-volatile, read-only firmware holding boot instructions/BIOS).
- Secondary Storage:
- Magnetic (HDD): Uses mechanical arms writing to spinning platters. High capacity but moving components are prone to wear.
- Solid State (SSD): Relies on NAND flash memory cells. No moving parts, faster read/write speeds, durable.
- Optical (CD/DVD/Blu-ray): Uses lasers to track pits and lands on a reflective surface layer.
4. Software & Languages
Bridges user intent to system execution profiles.
4.1 Operating Systems & Utility Programs
The Operating System (OS) manages memory allocation, file directories, user interfaces, security permissions, peripherals, and **interrupt routing handlers**.
4.2 Program Languages & Translators
- High-Level Languages: Human-readable source profiles (e.g., Python, Java). Portable across different system layouts.
- Low-Level Languages: Hardware-specific implementations including Assembly language or direct machine code.
| Compiler | Interpreter | Assembler |
|---|---|---|
| Translates high-level source code completely in one pass, outputting an executable file. | Translates and executes high-level source code line-by-line. Stops immediately at errors. | Converts low-level Assembly code into raw executable machine code blocks. |
5. Automated & Emerging Technologies
Examines interactive autonomous frameworks.
5.1 Automated Systems
Automated loops use input sensors (e.g., temperature, pressure, infra-red) to pass raw metrics to a microprocessor. The processor compares these readings against preset criteria and directs action parameters to physical output actuators (e.g., valves, pumps, motors).
5.2 Robotics & Artificial Intelligence (AI)
Robotics: Mechanical systems that feature a structured physical body, programmable logic control, and sensory perception capabilities.
AI: Algorithms designed to mimic human cognitive processes. Machine learning configurations rely on large datasets to train neural networks to identify patterns and refine performance metrics dynamically over time.
6. Algorithm Design & Problem-Solving
Algorithms define unambiguous, step-by-step instructions for solving specific problem sets.
6.1 Verification vs Validation
- Validation: Automated checks to verify input data matches acceptable criteria boundaries (e.g., range checks, length checks, type checks, presence checks).
- Verification: Checks to confirm that data matches its source entry exactly without transcription errors (e.g., double-entry verification, visual checks).
6.2 Test Data Selection Types
- Normal Data: Standard values that sit safely within expected parameters to verify structural stability.
- Abnormal/Erroneous Data: Out-of-bounds metrics designed to test error handling rules.
- Extreme Data: The lowest and highest boundaries of valid ranges (e.g., 0 and 100 in a 0–100 boundary condition).
- Boundary Data: Values immediately adjacent to valid range limits (e.g., -1 and 101 to check rejection rules).
6.3 Standard Searching & Sorting Algorithms
- Linear Search: Evaluates every index element sequentially from the start until the target element is found or the array ends.
- Binary Search: Requires a sorted array. Repeatedly divides the search space in half by comparing the midpoint to the target value. Highly efficient.
- Bubble Sort: Steps through a list multiple times, comparing adjacent items and swapping them if they are out of order, until a complete pass occurs without any swaps.
7. Pseudocode & Programming
The standard reference framework for logic design inside the CAIE curriculum evaluation track.
7.1 Standard Pseudocode Constructs
// 1. Variable Assignment and Declaration
DECLARE Age : INTEGER
Age <- 16
// 2. Conditional Branch Structures
IF Age >= 18 THEN
OUTPUT "Access Granted"
ELSE
OUTPUT "Access Denied"
ENDIF
// 3. Counting Loop Structure
FOR Count <- 1 TO 10
OUTPUT Count
NEXT Count
// 4. Conditional Loop Structure
WHILE Age < 18 DO
Age <- Age + 1
ENDWHILE
7.2 Array Multi-Dimensional Structures
Arrays act as continuous data blocks containing elements of identical data types accessed via index pointers (e.g., Names[1 TO 30]).
8. Databases & SQL
Structured query mechanics for organizing relational data tables.
A database uses fields (columns representing single properties) and records (rows tracking comprehensive object items). A Primary Key guarantees that every row record features a unique identifying value.
8.1 Structured Query Language (SQL) Foundations
SELECT StudentName, TestScore
FROM SchoolTable
WHERE TestScore >= 80
ORDER BY TestScore DESC;
9. Boolean Logic & Gates
Hardware logic gate evaluations track standard binary processing routing rules.
9.1 Core Logic Gates truth parameters
| Gate Type | Boolean Logic Statement Profile | Output Status Condition |
|---|---|---|
| AND | \( \text{Output} = A \cdot B \) | Outputs 1 only if BOTH input channels are 1. |
| OR | \( \text{Output} = A + B \) | Outputs 1 if AT LEAST ONE input channel is 1. |
| NOT | \( \text{Output} = \overline{A} \) | Inverts input status. |
| NAND | \( \text{Output} = \overline{A \cdot B} \) | Outputs 0 only if BOTH inputs are 1. Inverse of AND. |
| NOR | \( \text{Output} = \overline{A + B} \) | Outputs 1 only if BOTH inputs are 0. Inverse of OR. |
| XOR | \( \text{Output} = A \oplus B \) | Outputs 1 only if inputs are DIFFERENT from each other. |